As published on Semiconductor Engineering
Dr. John Hoffman, Computer Vision Engineering Manager of CyberOptics, discusses with Ed Sperling of Semiconductor Engineering some of the growing challenges with wafer bump inspection and metrology while ensuring reliability and yield remain consistent.
ES: Hi, I am Ed Sperling, and I am the Editor-in-Chief of Semiconductor Engineering. I am here with John Hoffman of CyberOptics. We are going to talk today about wafer bump inspection. John, as we go forward into shrinking down to the next nodes, as we move into advanced packaging, wafer bumps are becoming much more important. What has changed? Why is it now suddenly part of everything, and what do we have to think about as we do the inspection?
JH: What is happening is everyone wants to make their processor smaller; everyone wants to fit more capability into smaller footprints, and they want to reduce size and packaging of the semiconductors in the past that taken up a lot of volume. They put a lot of the packaging technology actually into the front end, so they are moving some of these OSAT processes, things that they would do to protect these chips, and actually they’re pushing that into the front end. Some places are putting conformal coatings on their chips right now, and protecting the chips from the environment, adding those protections in. Then the other fact that is driving this is chiplets. Because the circuits are getting so large and so complicated, they are segregating that out into these smaller chips. Now you want to package all of that together in as small of a package as possible. For all these reasons, they are putting bumps on silicon, and then directly attaching silicon to other silicon. The back-end semiconductor packaging inspection market is a market we have been in now for five plus years, and that market is still robust. Iit is still growing, however, a lot of that technology that is in that market is now getting pushed into what we have been calling, mid-end.
ES: These bumps are basically connections between these two chips, right, or between multiple chips? You really want to be able to say this is where the current is going to be flowing between the chips.
JH: Exactly. What in the past would have been a packaged unit with a lead heading out onto a circuit board, now they are trying to connect the dye directly to each other, and they want to do that by using as small a space as possible, and at the least volume as possible. They are doing that with these small bumps, and then they are marrying the silicon directly to each other, laying them on top of each other. Small wafer pieces – two pieces of silicon, and then mating them together so they have the electrical and physical contact to keep them mated while they go on and get more packages around them downstream. A way to think about this, is they are taking things that in the past would have been done by the back-end community, and pushing those processes closer to the front end. They still need those inspection capabilities in this mid-end area, which is what we are calling the market.
ES: As you do this, you have to connect these bumps exactly together, right? So, any differences in terms of height, in terms of something missing out of the bump, because it did not print right, that can cause an issue in terms of reliability.
JH: That becomes the big question. What are your critical measurements that you need to make, such that you know that when you take this die and marry it to this die, and some process downstream that they will, in fact, mate together properly. That you’ll have the 1,000 possible connections between those all, electrically solid, physically solid, because in some cases you’re using that as kind of a mortar between these two pieces, the glue that’s holding them together. What happens then is we have critical measurements of interest. The biggest measurements of interest are coplanarity and bump height. Are all these bumps aligned consistently? You do not want massive variability between these bumps.
ES: Give us an idea about how big the bumps really are. What are we looking at in terms of size?
JH: Anywhere from 20-micron diameter to 200-micron diameter. Then the pitch, the distance between the bumps, is anywhere from 40-microns to, well, we have seen some where they are a millimeter, which is a little unusual.
ES: As you go through a fairly large chip these days at an advanced node, how many bumps are you actually inspecting?
JH: Millions per wafer. The bumps that we are talking about inspecting in our mid-end systems, they are actually inspecting the wafers. The wafers will have a million to 10 million bumps on them.
ES: There’s been talk about 100% inspection on these bumps, is that even possible?
JH: Absolutely, we believe so. We have demonstrated this to several customers/potential customers that we can do 100% inspection of these bumps, with our NanoResolution Multi-Reflection Suppression™ (MRS™) sensor in our WX3000™ inspection and metrology system. It’s challenging and it is not easy. It’s taken us a couple of years to get to the point where we’re able to do that, but at this point we have the technology mature enough that we’re able to measure 100% of the bumps.
ES: You have a lot of data coming out of that because you are doing so much inspection, if you’re talking millions of bumps, you’ve got lots and lots of data. How do you go through that? How do you find out what is going to be a problem? What isn’t going to be a problem? What is a latent defect in one and what is acceptable?
JH: There are multiple steps in this process where there is a massive amount of data reduction occurring. The very first process, very first step, we have these very high-resolution cameras collecting data at hundreds of frames per second. From that, we generate a bunch of height data and 2D inspection data. We pass that off to the OEM. By OEM, my group makes the sensors and we sell the sensors to OEMs, who then integrate these sensors into material handling systems. We are in multiple different markets.
We have our OEMs who are dealing with and creating the wafer handling systems and the various material handling systems and the vacuum chucks. They are responsible for all of that. We generate this massive amount of data, a large amount of height data and 2D data that we pass on to the OEM. Now it is up to the OEM software to figure out how to reduce that further. We collaborate a lot with these people, what we’ve done with some of our OEMs, is we’ve proposed a number of summary measures that go along, and we’ve given them summary measurement algorithms that go along with these height maps. We will pass them a height map, and then we’ll also pass them an algorithm that will take this height map, find all the bumps, and for each bump we are going to give you five measurements of that bump which characterize that bump. It will be the height of that bump above the substrate, it will be the XY position of that bump, and it might be the diameter of that bump. There might be four measurement numbers for each bump that we pass on to the OEM, and now it is up to the OEM and the customer to say, all right, now customer, how can we further compress this data? Because if you are going to have 50 million data points per wafer, that might be too much data for you to store, what kind of metrics are important for you and for your process that you need to store long term so that you can understand how your processes are changing over time.
ES: What happens as the bump density increases? Companies like Intel are now talking about going down into the angstrom range. Will the current technology be able to detect all this stuff? Will they be able to see all the anomalies that you have made and outliers you are trying to find?
JH: We need to be clear about these measurements. The angstrom comment – that is talking about the logic circuits and the logic gates, and that is not what we are inspecting. We are not capable of inspecting down to that type of resolution. We are using optical sensors. The spatial resolution of our sensors is three-micron spatial resolution. We can easily inspect features that are 8 pixels across and 25 microns. We can easily inspect features of that size. In mid-end, where we are looking at bumps, like the way they are getting IO off the chips; those sizes of features are where they are at right now in the 20-micron range. There are some people pushing down to the 10-micron size. What that does is if you go from 20 microns down to 10 microns, all things being equal, we have to go from a 3-micron resolution to a 1.5-micron spatial resolution. On a 300-millimeter wafer, we are going to have to quadruple the amount of data that we collect, and that becomes a big challenge. Because if I am going to quadruple the amount of data I collect, the customer does not want to take four times as long, so how do we accomplish that? Well, we accomplish that with bigger cameras, faster cameras, better material handling, all of those things come into play, to try to keep the speed up.
ES: What is the difference with reflectivity when you are dealing with a material like silicon carbide versus bulk silicon?
JH: Silicon carbide ends up being somewhat specular, while silicon ends up being highly specular. There is a difference because of the silicon carbide targets, you can get some diffuse return and the polished silicon is acting like a mirror. For our mid-end product line, we have the capability of inspecting both diffuse and specular surfaces. What we would do in a situation like that, is we would adjust the lighting levels and the channels to make sure that we are getting the right signal in the right channels, and then combine them all after the fact. One way to think of it is a multimode sensor, we were able to measure specular surfaces and a diffuse surface. We have these independent channels and we can combine all that into a single height map and 2D image that we then present to the OEM. We can then create the algorithms to exploit that information for whatever interest the end user is interested in.
ES: As we move into finer and finer geometries, do those bumps get smaller, shorter? How does that change?
JH: Both. They are getting smaller and they are getting shorter. If you can get them smaller and shorter, you can make the dye smaller as well, and still have the same amount of IO coming out. If you shrink the feature size by half, and if you shrink the inner bump spacing by half, that is going to require us to collect four times as much data. Our challenge is to just kind of keep up with that, everything shrinking, keeping up with sensors that can resolve down at the finer and finer levels, and keep up with the speed of the of the fab.
ES: From an algorithm standpoint, your signal to noise ratio actually goes down on each new node that you are going to, right?
JH: That is the case if you stay with a fixed sensor, but if the nodes shrink by 50%, and we have a sensor with twice the amount of resolution, then we have the basically the same amount of signal. However, we have four times as much data to process. We’ve demonstrated the ability to keep up with these node changes. We have been through a number of these node changes in the SMT world, as they move from metric 0402 to metric 0201 to metric 01005. They are getting down to components that they are placing on circuit boards that are hundreds of microns in size. That has required us to refine our algorithms continually to get them faster, or to beef up our hardware. We have multiple ways we can attack these problems. One is to try to optimize the algorithms to make them faster than they already are, which is something we have done, or just put them on beefier hardware and just double the hardware speed. Because the whole electronics world is moving to smaller and smaller components, we get to exploit that in our sensors. We can have beefier and beefier computers with the same amount of power consumption and keep up.
ES: So, going back to something you mentioned before, why is 100% inspection so important these days?
JH: In any manufacturing process, the amount you inspect is proportional or related to how mature your process is. If you have your process completely dialed in, 100% reliable, you can maybe get by with just checking sporadically. You can do spot checks to make sure that your process is still as dialed in as you think it is, and that is good enough. But if you’re having yield issues. If you aren’t able to get 100% yield, then you want to have strategies for capturing failures as early as possible to help reduce the cost of yield failure. Particularly when we start talking about stacked die. If you have 50 different components, 50 different chiplets all stacked together into one large complicated package, that starts becoming a very expensive proposition to realize at the very end that everything didn’t get assembled properly. One way that people are doing that is to move to 100% inspection. Now I am going to inspect 100% of my chips. Because a common failure mode is if your chips are too warped or if the bumps are not planar, now that is just a kind of guaranteed failure. If you can catch that early, that is going to reduce your loss further downstream. You would rather get catch that loss upstream. The exact details of exactly where to inspect and how much, obviously is going to be a function of the particular manufacturing environment that these inspections are occurring in. We are seeing a lot of interest in the market and in 100% inspections of these bumps. This tends to be a failure point and failure mode for the assembly process of these things.
ES: If you think about this in terms of manufacturing, where they had front end of line, middle of line, which is sort of new, and then back end of line, this is really shifting left on that flow, right?
JH: Yes, some of these back-end processes are moving up towards and into the fab. I mentioned at one point the addition of conformal coating in the fab. These bumps are being added in the fab. The fabs are now doing inspections that in the past, they might not have had done.
ES: John Hoffman. Thanks for a great explanation.
JH: You are welcome.