Metrology for Wafer-Level and Advanced Packaging Processes

By: Tim Skunes, CyberOptics VP of R&D (as published on Chip Scale Review)

Advanced packaging (AP) and wafer-level packaging (WLP) continue to be among the most dynamic and rapidly evolving areas of semiconductor development and manufacturing. Most of these new AP/WLP processes take some advantage of the third dimension, going vertical to continue packing more computing power into less space while circumventing the difficulties posed by further reductions in two-dimensional size. Packaging stacks include various configurations of single or multiple chips, interposers, flip chips and substrates, but in almost all cases, they rely on some form of bump to make the vertical connections between these components.