By: Dr. Subodh Kulkarni, CyberOptics CEO (as published on Semiconductor Engineering)
We’ve previously identified the convergence occurring between surface mount technologies (SMT), used to connect packaged semiconductor devices on printed circuit boards, and advanced packaging (AP) technologies, in which connections between the semiconductor devices and to the outside world are incorporated in the packaging process using front-end-like, wafer-or panel-based manufacturing processes. What implications does this convergence have for inspection and metrology techniques used to control the process, ensure yields and maximize profitability?
The requirements for inspection and metrology are controlled primarily by the size, shape, and number of features. Here, we are looking at three-dimensional features that range from 10µm to 100µm size and may number in the tens of millions per wafer. Above all, inspection and metrology systems must have the basic measurement capability – resolution, sensitivity, accuracy and precision – needed to provide meaningful measurements. Once those criteria are met, they must have the speed to keep up with the manufacturing process – typically 25-50 300 mm wafers per hour. All else equal, more measurement per unit of time means lower cost per measurement and potentially greater profitability for the process as a whole.