Improving EUV Process Efficiency

By: Mark Lapedus, Executive Editor for Manufacturing, Semiconductor Engineering (as seen on Semiconductor Engineering)

The semiconductor industry is rethinking the manufacturing flow for extreme ultraviolet (EUV) lithography in an effort to improve the overall process and reduce waste in the fab.

Vendors currently are developing new and potentially breakthrough fab materials and equipment. Those technologies are still in R&D and have yet to be proven. But if they work as planned, they could boost the flow and present a challenge to the current vendor base.

For more than a decade, there was concern about whether EUV would ever make it into production. Since then, it has been adopted by leading-edge foundries at 7nm, with 5nm in R&D. But EUV still faces some challenges. At current and future nodes, for example, EUV processes can potentially cause defects in chips. In addition, the process flow itself is relatively inefficient, where new and expensive materials are wasted.

In a generic process flow, wafers are inserted into a system called a coater/developer, sometimes called a wafer track. Then, a photoresist, a light-sensitive material used to pattern chips, is poured onto a wafer. The wafer is spun at high rates, causing the resist to cover the wafer. But most of the resist material falls off the wafer and is wasted.

From there, the wafers are transported from the coater/developer to a lithography scanner, which exposes the resist with light. This creates patterns on the wafer based on a given IC design. Then, the wafers are developed and transported to other equipment in the fab for processing.

This process is used for traditional optical lithography as well as EUV. But EUV is different and more expensive than optical lithography. The flow works in both cases, yet in R&D, the industry is exploring some novel and breakthrough approaches to improve the EUV process. Among them:

– Next-generation EUV resists. Several entities are developing new resists that promise to outperform the current materials.

– Resistless lithography. Paul Scherrer Institute is exploring EUV without using a resist.

– Dry resist. Lam Research recently announced a dry resist technology, which is in R&D and targeted for 3nm. For this, various compounds are processed in a chemical vapor deposition (CVD) system, which creates an EUV resist. Instead of spin coating, the resist is deposited on the wafers in the CVD system, which reduces resist waste in the fab.

Dry resist technology is especially noteworthy. If it works, the technology could displace or become a viable alternative to today’s coaters/developers from TEL and Screen. Potentially, dry processes also enable new EUV resists. But changing the traditional flow isn’t simple in today’s risk-averse and cost-conscience environment. And so, these and other technologies face some challenges to move into the fab.

The traditional flow
Today’s semiconductor fabs are automated facilities that process wafers using a multitude of different equipment in a cleanroom. It’s a complex process. To make an advanced logic device, the wafer undergoes anywhere from 600 to 1,000 steps — or more.

Inside the fab, many critical steps occur in the lithography cell, where lithography tools work side-by-side with coaters/developers or wafer track systems to process, pattern and develop the chips on a wafer.

The lithography and wafer track equipment markets are sizable businesses. In 2020, the lithography equipment market is expected to reach about $11 billion, up 4% over 2019, according to Bob Johnson, an analyst at Gartner. The figures include optical and EUV.

In 2019, the wafer track equipment market is projected to reach $2 billion to $2.1 billion, compared to $2.26 billion in 2018, Johnson said. TEL is the largest wafer track supplier, followed by Screen and SEMES, he said.

For years, chipmakers used optical lithography tools to pattern the features in chips. The most advanced scanners use 193nm wavelength light. With the help of multiple patterning, chipmakers have extended 193nm optical lithography tools down to 10nm and 7nm. But at 5nm, it’s too unwieldly and expensive to use the traditional lithographic techniques.

“Trying to print 50nm, 40nm or 30nm features is an inherently difficult task for 193nm lithography,” said Aki Fujimura, chief executive of D2S. “Using EUV at 13.5nm wavelengths should make it easier and more viable.”

And that’s where EUV fits in. EUV simplifies the process and enables chipmakers to pattern the most difficult features at 7nm and beyond. Today, ASML is shipping its latest EUV scanner. Using a 13.5nm wavelength, the system enables 13nm resolutions with a throughput of 170 wafers per hour (wph).

In a fab, meanwhile, the lithography process flow hasn’t changed in years, whether it’s optical or EUV. The big difference is that optical lithography uses optical-based scanners. EUV is different and uses EUV-based scanners.

In the flow, the wafers undergo a preparation process. Then the wafers are moved into a coater/developer or a wafer track and EUV resist materials are inserted in the system. EUV resists are supplied by resist makers like Inpria, JSR and others.

Nonetheless, a wafer track performs what is commonly called a spin coating process. “You take the wafer and pour the liquid photoresist on it in a puddle,” said Chris Mack, CTO of Fractilia. “Then, you spin the wafer at a very high speed. The resist spins off the sides, and a little film stays on the wafer. Maybe 70% to 90% of the resist ends up going down the drain with some solvents, which are not friendly. It also costs money to throw them away.”

On the plus side, track systems are fast. For optical and EUV, the most advanced wafer track systems can process 300 wph.

The main goal of spin coating is to obtain the desired resist thickness on the wafer. “The final resist thickness varies as one over the square root of the spin speed, and is roughly proportional to the liquid photoresist viscosity,” Mack wrote on his lithography blog site.

Then, the wafer undergoes a pre-bake process, which removes excess solvent on the substrate. From there the wafers are transported to the lithography tool, which patterns them based on a given recipe. And finally, the wafer moves back to the same track system for development.

“The developer dissolves the parts of the resist, and you get your pattern,” Mack explained.

New approaches
For years, the industry has been developing new ways to develop and deposit resists beyond spin coating. Some technologies are in R&D. Others have failed.

Any new technology must meet certain criteria. “At the end of the day, it must have high throughputs to be competitive with spin-on processes,” said Douglas Guerrero, senior technologist at Brewer Science.

All told, coaters/developers will remain the dominate technology for the foreseeable future, although some of the newer technologies are worth watching.

For example, Paul Scherrer Institute, an R&D organization, recently described a resistless technology for EUV. For years, the industry has been working on various forms of resistless lithography to avoid using resists.

In traditional lithography, the resist is designed to produce patterns with high resolution and low defects. That’s not always the case with EUV. In the EUV process, photons hit a resist and cause a reaction. But there might be a new and different reaction during each event. And so EUV is prone to unwanted variations, sometimes stochastic effects.

If there is a mishap in the EUV process, the chip could suffer from stochastic-induced failures or defects. Generally, the industry blames the resists for the stochastics, but variations also can occur with the other parts of the process.

That is why resistless lithography is appealing. It sidesteps the stochastic effects. Resistless lithography, however, isn’t a mainstream technology. At this point it is confined to niche markets.

In resistless lithography, hydrogen atoms are formed on a silicon surface. In effect, the hydrogen atoms act as the resist. Then, using a scanning tunneling microscope (STM), the tip injects electrons on the surface, which breaks the bonds and forms patterns on the structure. This is called hydrogen depassivation lithography (HDL).

Instead of using an STM, Paul Scherrer Institute performed the same process using EUV. For this, EUV light exposed a hydrogen-terminated silicon surface, enabling patterns down to 5nm. “We demonstrated that we can perform patterning without a photoresist,” said Yasin Ekinci, head of the Advanced Lithography and Metrology group at Paul Scherrer Institute. “Our process does not involve a resist, which is, conventionally, the core concept of photolithography. It starts with the hydrogen passivation of the Si surface. The wafer is transferred to a EUV interference lithography system. During this time, the wafer is already oxidized partially. The wafer is exposed to EUV radiation, which induces further oxidation of the surface. By using the chemical etch contrast of the partially oxidized and EUV-induced surface oxide, we could etch up to 30nm into the Si and obtained patterns down to 70nm hp.”

Other approaches also are being pursued, which have a better chance from moving out of R&D. Dry resist is one such approach. “This is not new,” said Dan Hutcheson, chief executive of VLSI Technology. “It’s been around for PCBs for around 40 years.”

In a PCB dry resist process, a seed layer is applied to a surface. A dry film is pasted on the surface using a laminator system, and then the surface is exposed to form a pattern.

Meanwhile, Lam is developing a more advanced dry resist technology in partnership with ASML and Imec. Dry resist is different than spin coating, which is considered a wet process. “The difference is that this is a some sort of a CVD or PVD process,” Hutcheson said. “It’s certainly interesting and revolutionary in concept from a deposition perspective. However, I have my doubts that it’s ready for manufacturing.”

CVD has been around for decades. In a CVD system, wafers are inserted into a system. Chemicals are injected into a process chamber in the system, which reacts to the wafer and forms thin layers of materials on the surface.

In Lam’s dry resist process, wafers are inserted in a dry resist deposition system. By combining various compounds, the deposition system creates an EUV resist in-situ. Then, the wafers are moved to an EUV scanner for exposure. Finally, the wafers move to a separate dry development system from Lam.

This process represents a 5X to 10X reduction in material waste and cost compared to spin coating. It also has other advantages. “By contrast if we go dry, we don’t need to worry about viscosity,” said Richard Gottscho, executive vice president and CTO of Lam, during the company’s recent public analyst meeting. “You have to worry about adhesion, but you can tailor the properties of the surface before you deposit your photosensitive material. Or you can tailor the properties of the material as you grow the thickness. And you have tremendous control over the thickness of that film as opposed to if you are spinning something on.”

Dry resist solves another issue. Advanced devices incorporate taller structures with high-aspect ratios. The patterns tend to collapse during the process. In dry resist, the patterns are less prone to collapse.

Originally, Lam developed this process for high-numerical aperture EUV, a next-generation EUV technology targeted for 2nm. Now, Lam is targeting the technology for 3nm, where it could work with today’s EUV scanners.

Dry resist has some challenges. Defectivity and throughput are still unknowns. “There are some real advantages of dry deposition because there is less waste,” Fractilia’s Mack said. “But in a sense, those things are secondary. The real question is, ‘Does this resist work well? Does it improve the dose-stochastic-variability trade-off?’”

But if Lam’s EUV resists are better than the current materials, the technology could change the landscape. “There is a lot of potential here,” said Harry Levinson, principal at HJL Lithography. “The interesting part is that you have these and other new resists. They could totally change the mix. This could be disruptive for vendors who make traditional resists and the equipment for spin coating.”

In response, Shin Nakagawa from the marketing department at Screen Semiconductor, a supplier of fab equipment, said: “The approach with dry resist has been studied in the past over several technology nodes. In many cases, the motivation was to eliminate the issues in traditional spin coat resist processes such as defects coming from the polymer resist or reduction of waste. A dry process typically has the advantage of less polymer-induced-defects and less chemical waste. Despite the conceptual advantage of dry processing, traditional spin coat processes have been used as a major technique by overcoming these advantages. Although we are watchful of further developments of dry resist technology as an alternative solution in the future, at this moment we believe that spin-on technology will still remain the industry standard for a while.”

TEL did not respond for comment.

Resist developments
Another way to improve the EUV process is to develop better EUV resists. For some time, several entities have been developing next-generation EUV resists, which are in R&D.

Generally, EUV resists fall into three different categories—chemically amplified resists (CARs), non-chemically amplified polymer resists, and metal-oxide resists.

Today, chipmakers are using CARs for EUV, but metal-oxide resists are gaining steam. Lam’s EUV resist falls under the metal-oxide category, according to Fractilia’s Mack.

Each resist type is different, with various tradeoffs. Regardless, EUV requires a robust resist with the proper dose, which enables patterns with fine resolutions.

It’s a complex formula. For example, using an EUV resist with a 30mJ/cm² dose, an EUV scanner with a 250-watt source has a throughput of 104 to 105 wph.

Today’s EUV resists are adequate for current chip production. “Resists are supporting the 7nm node today,” Levinson said. “There has been considerable progress in developing new resists to support the 30nm-pitch target of the 5nm node, particularly since people are now giving serious consideration to resists with exposure doses higher than 20mJ/cm².”

Still, the industry may require new or improved EUV resists at 5nm and beyond. But resist development is a challenging endeavor for any node. “The resist challenges in EUV in order of importance are stochastics, roughness, resolution and sensitivity,” Brewer’s Guerrero said.

As stated, EUV processes are prone to stochastics. They also can lead to pattern roughness. Both issues can cause defects in chips. For various reasons, the stochastics become more problematic at each node.

One way to deal with the problem is to boost the EUV source power to 500 watts or 1,000 watts. That way, you can use a higher dose and ensure yield. But 500-watt (or more) sources are still in R&D.

Developing better resists is another solution. Today’s CARs continue to improve, but they may run out of steam. Metal-oxide EUV resists are gaining momentum because they are more efficient than CARs.

“There is a lot of noise at the molecular level in chemically amplified resists, so we may be approaching the limits for this chemical platform that has served us so well,” HJL Lithography’s Levinson said. “Of the non-chemically amplified resists, the metal-oxide materials have been the center of most activity. These materials are negative tone, which makes them suitable for metal layers, but are problematic for patterning contacts and vias. Regardless of resist type, the ranges of photoelectrons and the secondary electrons that mediate the chemistry could be limiting resolution, and this needs more study to solve.”

Other issues can also crop up in the fab. Today, much of the variation in resist thicknesses needs to be compensated using simulation and design process technology co-optimization (DTCO).

“When we looked at three different etch thicknesses after litho or etch, and if we did different dose compensations, we could get good uniformity on different resist thicknesses after litho,” said David Fried, vice president of computational products at Lam Research/Coventor. “But what you see is that in the after etch, uniformity is quite poor and the standard deviation of the results increases for the thicker resists. So a process might be quite good after litho, but quite poor after etch. If you turn that around and use simulation for your after-etch target, the standard deviation drops significantly. So you can go to higher thickness resists, reduce the variation and distributions, and still hit your target with higher resists.”

There are other issues. “As with any area of the fab, particle contamination can be an issue for EUV processes. It’s critical to be able to identify, monitor and troubleshoot particles quickly and efficiently. For EUVL tools, the ability to monitor particles in-line can significantly improve EUVL tool yield and productivity,” said Tim Skunes, vice president of R&D at CyberOptics. “For example, an in-line particle sensor can be installed at the vacuum line in-between the EUV process chamber and the vacuum pump, saving significant time compared to current methods of sending a monitor dummy reticle into the EUV system to check for particles before and after sending the reticle into the EUVL.”

Conclusion
Clearly, EUV is here and in production, but there’s always room for improvement. New resists, deposition and other techniques may help matters.

It’s always difficult to make a big change in the fab because chipmakers are risk-averse. They also worry about costs. But they also constantly are looking for new solutions to get a leg up on the competition.